This invention relates to a control of the instruction pipeline in a data control system.
In a data processing system having an instruction pipeline, each pipeline has a plurality of segments and each instruction is allotted for execution, part by part to the segments. The pipeline processing of instructions in a data processing system of the type as described above is disclosed in, for example, U.S. Pat. No. 3,840,861 issued Oct. 8, 1974 to G. M. Amdahl et al entitled "Data processing System having an Instruction Pipeline for Concurrently Processing a Plurality of Instructions". In the known pipeline processing, the operations of the respective segments are controlled on the basis of the same clock signal having a specific frequency and several cycles of the reference clock signal are supplied to each segment for execution of allotted processes at generally different steps in each instruction by that segment. The period of one cycle is determined depending on the time required for each segment to execute its work to be completed in one cycle. Since the time depends on the segments, the period of one cycle must be determined to be equal to or larger than the maximum one of the times required for the respective segments. Accordingly, this degrades the processing efficiency of the whole system. For example, in the case where the period of one cycle must be at least 100 ns for a segment A while 150 ns for a segment B and where the segments A and B require, respectively five cycles and three cycles for execution of the allotted parts of an instruction, the period of one cycle of the reference clock signal by which the operation of both the segments A and B are controlled must be equal to or longer than 150 ns. Since all the segments must finish their processing before the pipeline processing starts execution of the next instruction, if both the segments A and B are controlled by the same reference clock signal having a period of 150 ns, the segment A finishes its processing in 150 ns.times.5=750 ns and the segment B in 150 ns.times.3=450 ns. Therefore, 750 ns is needed for one operation cycle. However, if the segment A is controlled by a reference clock having a period of 100 ns and the segment B by a reference clock having a period of 150 ns, then the segments A and B finish their processing in 100 ns.times.5=500 ns and 150 ns.times.3=450 ns, respectively so that one operation cycle can be reduced to 500 ns. This saves 250 ns.
Also, the period of one cycle required for each individual segment to execute its process which includes reading of information from a memory must be longer than where it does not include reading of any information. Accordingly, in a mini-computer such as a machine-control computer which is relatively simple in construction and flexible in use, the timing is performed in such a manner that the clock signal is temporarily held at the time when the reading from the memory is started and the clock signal is resumed after finishing the reading from the memory. If a pipeline processing is performed in this manner, the start of the memory reading commanded by a segment holds the clock signal so that the operations of other segments which are controlled by the same clock signal and do not need the memory reading are also held, with the result that the processing time is prolonged.